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Espressif Systems /ESP32-S3 /DMA /IN_INT_ENA_CH0

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Interpret as IN_INT_ENA_CH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_DONE)IN_DONE 0 (IN_SUC_EOF)IN_SUC_EOF 0 (IN_ERR_EOF)IN_ERR_EOF 0 (IN_DSCR_ERR)IN_DSCR_ERR 0 (IN_DSCR_EMPTY)IN_DSCR_EMPTY 0 (INFIFO_FULL_WM)INFIFO_FULL_WM 0 (INFIFO_OVF_L1)INFIFO_OVF_L1 0 (INFIFO_UDF_L1)INFIFO_UDF_L1 0 (INFIFO_OVF_L3)INFIFO_OVF_L3 0 (INFIFO_UDF_L3)INFIFO_UDF_L3

Description

Interrupt enable bits of Rx channel 0

Fields

IN_DONE

The interrupt enable bit for the IN_DONE_CH_INT interrupt.
IN_SUC_EOF

The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
IN_ERR_EOF

The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
IN_DSCR_ERR

The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
IN_DSCR_EMPTY

The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
INFIFO_FULL_WM

The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.
INFIFO_OVF_L1

The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
INFIFO_UDF_L1

The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
INFIFO_OVF_L3

The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
INFIFO_UDF_L3

The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data